Abstract

An arithmetic logic unit (ALU) is at the heart of a modern microprocessor, and the adder cell is the elementary unit of an ALU. In this paper, we design an ALU which mainly consists of two adders. This design takes advantage of Adaptive Logic Module (ALM) architecture. And we employ verilog to describe the ALU. So the design code can be used as a soft-core. To efficiently implement adders, we directly use the Library of Parameterized Modules (LPM) megafunction to configure the desired adders. In addition, our ALU is two-stage pipelined design. As a result, simulations show the design is credible and stable.